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company confidential ? 1 data sheet ? 2011?2012 by atheros communications, inc. all rights reserved. atheros?, atheros driven?, align?, atheros xr?, driving the wi reless future?, intellon?, no new wires?, orion? , plc4trucks?, powerpacket?, spread spectrum carr ier?, ssc?, rocm?, super a/g?, super g?, super n?, the air is cleaner at 5-ghz?, total 802.11?, u-nav?, wake on wireless?, wireless future. unleashed now.?, and xspan?, are registered by atheros communications, inc. atheros sst?, signal-sustain technology?, ethos?, install n go?, ique?, rocm?, amp?, simpli -fi?, there is here?, u-map?, u-tag?, and 5-up? are trademarks o f atheros communications, inc. the atheros logo is a registered trademark of atheros commu nications, inc. all other trademarks are the property of their respective holders. subject to change without march 2012 ver. 2.1 ar8035 integrated 10/100/1000 mbps ethernet transceiver general description the ar8035 is part of the arctic family of devices - which includes the ar8031, ar8033, and the ar8035. it is atheros? 4 th generation, single port 10/100/1000 mbps tri-speed ethernet phy. it supports rgmii interface to the mac.? the ar8035 provides a low power, low bom (bill of materials) cost solution for comprehensive applications including consumer, enterprise, carrier and home networks such as pc, hdtv, gaming machines, blue-ray players, iptv stb, media players, ip cameras, nas, printers, digital photo frames, moca/homeplug (powerline)/eoc/ adapters and home router & gateways, etc. the ar8035 integrates atheros latest green ethos ? power saving technologies and significantly saves power not only during work time, but also during overtime. atheros green ethos ? power savings include ultra-low power in cable unplugged mode or port power down mode, and automatic optimized power saving based on cable length. furthermore, the ar8035 supports wake-on-lan (wol) feature to be able to help manage and regulate total system power requirements. the ar8035 embeds cdt (cable diagnostics test) technology on-chip which allows customers to measure cable length, detect the cable status, and identify remote and local phy malfunctions, bad or marginal patch cord segments or connectors. some of the possible problems that can be detected include opens, shorts, cable impedance mismatch, bad connectors, termination mismatch, and a bad transformer. the ar8035 also integrates a voltage regulator on chip. it reduces the termination r/c circuitry on both the mac interface (rgmii) and line side. the ar8035 supports ieee 802.3az energy efficient ethernet (eee) standard and atheros proprietary smarteee, which allows legacy mac/soc devices without 802.3az support to function as the comple te 802.3az system. the key features supported by the device are: n 10base-te phy supports reduced transmit amplitude. n 100base-tx and 1000base-t use low power idle (lpi) mode to turn off unused analog and digital blocks to save power while data traffic is in idle. features n 10base-te/100base-tx/1000 base-t ieee 802.3 compliant n supports 1000 base-t pcs and auto- negotiation with next page support n supports rgmii interface to mac devices with a broad i/o voltage level options including 2.5v, 1.8v and 1.5v, and is compatible with 3.3v i/o n rgmii timing modes su pport internal delay and external delay on rx path n error-free operation up to 140 meters of cat5 cable n supports atheros latest green ethos ? power saving modes with internal automatic dsp power saving scheme n supports 802.3az (energy efficient ethernet) n fully integrated digital adaptive equalizers, echo cancellers, and near end crosstalk (next) cancellers n supports wake-on-lan (wol) to detect magic packet and notify the sleeping system to wake up n a robust cable discharge event (cde) tolerance of 6kv n a robust surge protection with 750v/ differential mode and 4kv/common mode n jumbo frame support up to 10kb (full duplex) n all digital baseline wander correction n automatic channel swap (acs) n automatic mdi/mdix crossover n automatic polarity correction n ieee 802.3u compliant auto-negotiation n software programmable led modes n multiple loopback modes for diagnostics free datasheet http:///
2 ? ar8035 integrated 10/100/1000 mbps ethern et transceiver atheros communications, inc. 2 ? march 2012 company confidential n cable diagnostic test (cdt) n single power supply: 3.3v n 5mm x 5mm. 40-pin qfn package ar8035 functional block diagra m dac waveshape filter echo canceller next canceller hybrid circut pga feed forward equalizer adc agc timing and phase recovery deskewer decision feedback equalizer symbol encoder symbol decoder auto- negotiation mii management registers dll trd[0:3] rgmii pma pcs trellis decoder rgmii
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 3 company confidential november 2011 ? 3 revision history date revsion details revision 2011/3/15 first release 1.0 2011/11/25 electrical characteristics n add a note under recommended operation conditions topside marking n add topside marking illustration 2.0 2012/3/1 electrical characteristics n change mdio tmdelay minimal value to 0 ns; typical value to 4 ns ordering information n remove ar8035-al1b industrial tray pack ordering 2.1
4 ? ar8035 integrated 10/100/1000 mbps ethern et transceiver atheros communications, inc. 4 ? november 2011 company confidential
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 5 company confidential november 2011 ? 5 table of contents general description ........................................ 1 features ............................................................ 1 ar8035 functional block diagram .............. 2 revision history ............................................. 3 table of contents ............................................ 5 1 pin descriptions ............................ 7 2 functional description ............... 13 2.1 transmit functions ................................ 14 2.2 receive functions .................................. 14 2.2.1 decoder modes ........................... 14 2.2.2 analog to digital converter ...... 14 2.2.3 echo canceller ............................. 14 2.2.4 next canceller .......................... 14 2.2.5 baseline wander canceller ....... 14 2.2.6 digital adaptive equalizer ....... 14 2.2.7 auto-negotiation ........................ 15 2.2.8 smartspeed function ................. 15 2.2.9 automatic mdi/mdix crossover 15 2.2.10 polarity correction ..................... 15 2.3 loopback modes .................................... 15 2.3.1 digital loopback ......................... 15 2.3.2 external cable loopback ........... 15 2.3.3 remote phy loopback .............. 16 2.4 cable diagnostic test ............................ 16 2.5 led interface .......................................... 16 2.6 power supplies ....................................... 18 2.7 management interface .......................... 19 2.8 atheros green ethos? .......................... 20 2.8.1 low power modes ...................... 20 2.8.2 shorter cable power mode ....... 20 2.8.3 hibernation mode ...................... 20 2.9 ieee 802.3az and energy efficient ethernet 21 2.9.1 ieee 802.3az lpi mode .............. 21 2.10 atheros smarteee ................................ 22 2.11 wake on lan (wol) ........................... 22 3 electrical characteristics ............ 23 3.1 absolute maximum ratings ................ 23 3.2 recommended operating conditions 23 3.3 rgmii characteristics ........................... 24 3.4 mdio characteristics ............................ 26 3.5 xtal/osc characteristics .................. 27 3.6 power pin consumption ...................... 28 3.7 typical power consumption parameters 29 3.8 power-on sequence, reset and clock . 30 3.8.1 power-on sequence .................... 30 3.8.2 reset and clock timing ............. 30 4 register descriptions ..................31 4.1 register summary ................................. 31 4.1.1 control ......................................... 32 4.1.2 status ............................................ 34 4.1.3 phy identifier [18:3] .................. 35 4.1.4 phy identifier [19:24] ................ 35 4.1.5 auto-negotiation advertisement 35 4.1.6 link partner ability (base page) 37 4.1.7 auto-negotiation expansion .... 38 4.1.8 next page transmit .................... 38 4.1.9 link partner next page ............. 39 4.1.10 1000 base-t control ................. 39 4.1.11 1000 base-t status .................... 41 4.1.12 mmd access address register 42 4.1.13 mmd access control register . 42 4.1.14 extended status .......................... 43 4.1.15 function control ......................... 43 4.1.16 phy-specific status .................... 44 4.1.17 interrupt enable .......................... 45 4.1.18 interrupt status ........................... 46 4.1.19 smart speed ................................. 47 4.1.20 cable diagnostic tester control 47 4.1.21 led control ................................ 48 4.1.22 cable defect te ster status ......... 49 4.1.23 debug port address offset ....... 49 4.1.24 debug port data ......................... 49 4.2 debug register descriptions ............... 50 4.2.1 rgmii rx clock delay control 50 4.2.2 rgmii tx clock delay control 50 4.2.3 hibernation control and rgmii gtx clock delay register ......... 51 4.2.4 100base-tx test mode select . 52 4.2.5 1000bt external loopback configure ...................................... 52
6 ? ar8035 integrated 10/100/1000 mbps ethern et transceiver atheros communications, inc. 6 ? november 2011 company confidential 4.2.6 rgmii_mode; test configuration for 10bt .............................................. 53 4.2.7 mmd3 (mdio manageable device address 3 for pcs) ..................... 53 4.2.8 mmd7 (mdio manageable device address 7 for auto-negotiation) 54 4.3 mdio interface register ....................... 54 4.3.1 pcs control 1 .............................. 54 4.3.2 pcs status 1 ................................. 56 4.3.3 eee capability ............................ 57 4.3.4 eee wake error counter ........... 57 4.3.5 wake-on-lan loc_mac_addr_o . 58 4.3.6 wake-on-lan loc_mac_addr_o . 58 4.3.7 wake-on-lan loc_mac_addr_o . 58 4.3.8 rem_phy_lpkb ............................ 59 4.3.9 smart_eee control1 ..................... 59 4.3.10 smart_eee control2 ..................... 59 4.3.11 smart_eee control3 ..................... 60 4.3.12 an status ..................................... 61 4.3.13 an xnp transmit1 ..................... 61 4.3.14 an xnp transmit2 ..................... 61 4.3.15 eee advertisement ..................... 62 4.3.16 eee lp advertisement ................ 62 5 package dimensions ................... 63 6 ordering information ................. 65 7 top-side marking ....................... 65
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 7 company confidential november 2011 ? 7 1. pin descriptions this section contains a package pinout for the ar8035 qfn 40 pin and a listing of the signal descriptions (see figure 1-1 ). the following nomenclature is used for signal names: the following nomenclature is used for signal types described in table 1-1 : table 1-1. nc no connection to the internal die is made from this pin n at the end of the signal name, indicates active low signals p at the end of the signal name, indicates the positive side of a differential signal n at the end of the signal name indicates he negative side of a differential signal table 1-2. d open drain ia analog input signal i digital input signal ih input signals with weak internal pull-up, to prevent signals from floating when left open il input signals with weak internal pull-down, to prevent signals from floating when left open i/o a digital bidirectional signal oa an analog output signal o a digital output signal p a power or ground signal pd internal pull-down for input pu internal pull-up for input
8 ? ar8035 integrated 10/100/1000 mbps ethern et transceiver atheros communications, inc. 8 ? november 2011 company confidential figure 1-1 shows the pinout diagram for the ar8035. note: there is an exposed ground pad on the back side of the package. figure 1-1. pinout diagram ar 8035 top view exposed ground pad on bottom 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31 32 36 35 34 33 25 40 39 38 37 17 18 19 20 21 22 23 24 13 14 15 16 trxp0 trxn0 trxp1 trxn1 trxp2 trxn2 trxp3 trxn3 gtx_clk rx_clk rx_dv rxd0 rxd1 rxd2 rxd3 tx_en txd0 txd1 txd2 txd3 mdc mdio led_act led_10_100 led_1000 clk_25m rstn xtli xtlo rbias lx vddh_reg vddio_reg avddl dvddl vdd33 avdd33 avddl avddl int
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 9 company confidential november 2011 ? 9 table 1-3. symbol pin type description mdi trxp0, trxn0 9, 10 ia, oa medi a-dependent interface 0, 100 transmission line trxp1, trxn1 12, 13 ia, oa medi a-dependent interface 1, 100 transmission line trxp2, trxn2 15, 16 ia, oa medi a-dependent interface 2, 100 transmission line trxp3, trxn3 18, 19 ia, oa medi a-dependent interface 3, 100 transmission line rgmii gtx_clk 33 i, pd rgmii transmit cloc k, 125 mhz digital. adding a 22 damping resistor is recommended for emi design near mac side. rx_clk 31 i/o, pd 125mhz digital, adding a 22 damping resistor is recommended for emi design near phy side. rx_dv 30 i/o, pd rgmii receive data valid rxd0 29 i/o, pd rgmii received data 0 rxd1 28 i/o, pd rgmii received data 1 rxd2 26 i/o, pd rgmii received data 2 rxd3 25 i/o, pd rgmii received data 3 tx_en 32 i, pd rgmii transmit enable txd0 34 i, pd rgmii transmit data 0 txd1 35 i, pd rgmii transmit data 1 txd2 36 i, pd rgmii transmit data 2 txd3 37 i, pd rgmii transmit data 3 management interface and interrupt mdc 40 i, pu management data clock reference mdio 39 i/o, d, pu management data, 1.5k pull-up to 3.3v/2.5v int 20 i/o, d, pd interrupt signal to syst em; default od-gate, needs an external 10k pull-up, active low; can be configured to i/o by register, active high. led led_act 21 i/o, pu parallel led output for 10/100/1000 base-t activity, active blinking. led active based upon po wer-on strapping. if pulled up ? active low, if pulled down ? active high led_1000 22 i/o, pu parallel led output for 1000 base-t link, led active based upon power-on strapping. if pulled up ? active low, if pulled down ? active high
10 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 10 ? november 2011 company confidential led_10_100 24 i/o, pu parallel led output for 10/100 base-t link. led active based upon power- on strapping of led_1000. if led_1000 is pulled up, this pin is active low; if led_1000 is pulled-down, active high. high, external pu 10 mbps low, external pu 100 mbps system signal group/reference clk_25m 23 o, pd 25 mhz clock output (default ). it can be 125, 62.5 or 50 mhz clock output rstn 1 i system reset, active low. re quires an external pull-up resistor xtli 5 ia crystal oscillator input. re quires a 27 pf capacitor to gnd. support external 25 mhz, 1.2v sw ing clock input th rough this pin. xtlo 4 oa crystal oscillator output; 27 pf to gnd rbias 7 oa external 2.37 k 1% to gnd to set bias current power lx 2 oa power inductor pin. add an external 4.7 h power inductor between this pin and pin 38. vddh_reg 8 oa 2.5 v regulator output. a 1uf capacitor connected to this pin vddio_reg 27 oa 1.5v/1.8v regulator output .if rgmii interface voltage level is 2.5v, connect this pin to pin 8 directly. avddl 6, 11, 17 p 1.1 v analog power input. connect to pin 38 through a bead dvddl 38 p 1.1 v digital core power inpu t. connect to power inductor and 10uf+0.1uf ceramic capacitors to gnd vdd33 3 p 3.3 v power for switching regulator avdd33 14 p analog 3.3 v power input for phy, from vdd33 through a bead - - exposed ground pad on back of the chip, tie to ground table 1-3. symbol pin type description
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 11 company confidential november 2011 ? 11 note: 0=pull-down, 1=pull-up note: power on strapping pins are latched during power-up reset or warm hardware reset. note: some mac devices input pins may drive high/low during power-up or reset. so phy power on strapping status may be affected by the mac side. in this case an external 10k pull- down or pull-high resistor is needed to ensure a stable expected status. note: when using 2.5v rgmii i/o voltage level, rx_clk can be pull-up or pull-down. table 1-4. phy pin phy core configuration signal description default internal weak pull- up/pull- down rxd0 phyaddress0 led_act, rxd[1:0] sets the lower three bits of the physical address. th e upper two bits of the physical address are set to the default, ?00? 0 rxd1 phyaddress1 0 led_act phyaddress2 1 rx_dv mode0 mode select bit 0 0 rxd2 mode1 mode select bit 1 0 led_1000 mode2 mode select bit 2 1 rxd3 mode3 mode select bit 3 0 rx_clk 1.8v/1.5v select the rg mii/rmii i/o voltage level 1: 1.8v i/o 0: 1.5v i/o 0
12 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 12 ? november 2011 company confidential note: plloff means ar8035 can shut down internal pll in power saving mode; in plloff mode, when the ar8035 enters power saving mode (hibernation), clk_25m output drops periodically, which saves more power. in pllon mode, clk_25m outputs continuously. table 1-5. mode[3:0] description 1100 rgmii, plloff, int; 1110 rgmii, pllon, int; others reserved
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 13 company confidential november 2011 ? 13 2. functional description the ar8035 is atheros's low cost gbe phy. it is a highly integrated analog front end (afe) and digital signal transceiver, providing high performance combined with substantial cost reduction. the ar8035 provides physical layer functions for half/full -duplex 10 base-te, 100 base-tx and 1000 base-t ethernet to transmit and receive high-speed data over standard category 5 (cat5) unshielded twisted pair cable. the ar8035 10/100/1000 phy is fully 802.3ab compliant, and supports the reduced gigabit media-independent interface (rgmii) to connect to a gigabit-capable mac. the ar8035 transceiver combines echo canceller, near end cross talk (next) canceller, feed-forward equalizer, joint viterbi, feedback equalizer, and timing recovery, to enhance signal performance in noisy environments. the ar8035 is a part of the arctic family of devices ? which includes the ar8031, the ar8033, and the ar8035. a comparison of these is shown below. table 2-1 shows a feature comparison across the ar8031, ar8033, and ar8035 family. note: ar8031, ar8033 is pin-to-pin compatible note: ** 10base-te, 100base-tx, 1000base-t will be supported note: *** 100base-fx, and 1000base-x will be supported table 2-1. ar8031, ar8033, ar8035 comparison feature ar8031 ar8033 ar8035 rgmii yes yes yes sgmii yes yes cu ethernet ** yes yes yes eee (802.3az) yes yes yes wake-on-lan yes yes yes serdes/fiber yes *** yes *** 1588v2 yes sync-e yes yes packaging 48-pin 48-pin 40-pin
14 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 14 ? november 2011 company confidential 2.1 transmit functions table 2-2 describes the transmit function encoder modes. 2.2 receive functions 2.2.1 decoder modes table 2-3 describes the receive function decoder modes. 2.2.2 analog to digital converter the ar8035 device employs an advanced high speed adc on each receive channel with high resolution, which results in better snr and lower error rates. 2.2.3 echo canceller a hybrid circuit is used to transmit and receive simultaneously on each pair. a signal reflects back as an echo if the transmitter is not perfectly matched to the line. other connector or cable imperfections, such as patch panel discontinuity and variations in cable impedance along the twisted pair cable, also result in drastic snr degradation on the receive signal. the ar8035 device implements a digital echo canceller to adjust for echo and is adaptive to compensate for the varied channel conditions. 2.2.4 next canceller the 1000 base-t physical layer uses all four pairs of wires to transmit data. because the four twisted pairs are bundled together, significant high frequency crosstalk occurs between adjacent pairs in the bundle. the ar8035 device uses three parallel next cancellers on each receive channel to cancel high frequency crosstalk. the ar8035 cancels next by subtracting an estimate of these signals from the equalizer output. 2.2.5 baseline wander canceller baseline wander results from ethernet links that ac-couple to the transceivers and from ac coupling that cannot maintain voltage levels for longer than a short time. as a result, transmitted pulses are di storted, resulting in erroneous sampled values for affected pulses. baseline wander is more problematic in the 1000 base-t environment than in 100 base- tx due to the dc baseline shift in the transmit and receive signals. the ar8035 device uses an advanced baseline wander cancellation circuit that continuously monitors and compensates for this effect, minimizi ng the impact of dc baseline shift on the overall error rate. 2.2.6 digital adaptive equalizer the digital adaptive equalizer removes inter- symbol interference at the receiver. the digital adaptive equalizer takes unequalized signals from adc output and uses a combination of feedforward equalizer (ffe) and decision table 2-2. encoder mode encoder mode description 1000 base-t in 1000 base-t mode, the ar8035 scrambles transmit data bytes from the mac interfaces to 9-bit symbols and encodes them into 4d five-level pam signals over the four pairs of cat5 cable. 100 base-tx in 100 base-tx mode, 4-bit data from the mii is 4b/5b serialized, scrambled, and encoded to a three-level mlt3 sequence transmitted by the pma. 10 base-te in 10 base-te mode, the ar8035 transmits and receives manchester-encoded data. table 2-3. decoder mode decoder mode description 1000 base-t in 1000 base-t mode, the pma recovers the 4d pam signals after accounting for the cabling conditions such as skew among the four pairs, the pair swap order, and the polarity of the pairs. the resulting code group is decoded into 8-bit data values. data stream delimeters are translated appropriately and data is output to the mac interfaces. 100 base-tx in 100 base-tx mode, the receive data stream is recovered and descrambled to align to the symbol boundaries. the aligned data is then parallelized and 5b/ 4b decoded to 4-bit data. this output runs to the mii receive data pins after data stream delimiters have been translated. 10 base-te in 10 base-te mode, the recovered 10 base-te signal is decoded from manchester then aligned.
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 15 company confidential november 2011 ? 15 feedback equalizer (dfe) for the best- optimized signal-to- noise (snr) ratio. 2.2.7 auto-negotiation the ar8035 device supports 10/100/1000 base-t copper auto-negotiation in accordance with ieee 802.3 clauses 28 and 40. auto- negotiation provides a mechanism for transferring information between a pair of link partners to choose the best possible mode of operation in terms of speed, duplex modes, and master/slave preference. auto-negotiation is initiated upon any of the following scenarios: n power-up reset n hardware reset n software reset n auto-negotiation restart n transition from power-down to power-up n the link goes down if auto-negotiation is disabled, a 10 base-te or 100 base-tx can be manually selected using the ieee mii registers. 2.2.8 smartspeed function the atheros smartspeed function is an enhanced feature of auto-negotiation that allows the ar8035 device to fall back in speed based on cabling conditions as well as operate over cat3 cabling (i n 10 base-t mode) or two-pair cat5 cabling (in 100 base-tx mode). by default, the smartspeed feature is enabled. refer to the register ?smart speed? on page 47 , which describes how to set the parameters. set these register bits to control the smartspeed feature: n bit [5]: 1 = enables smartspeed (default) n bits [4:2]: sets the number of link attempts before adjusting n bit [1]: timer to determine the stable link condition 2.2.9 automatic mdi/mdix crossover during auto-negotiation, the ar8035 device automatically determines and sets the required mdi configuration, eliminating the need for external crossover cable. if the remote device also implements automatic mdi crossover, the crossover algorithm as described in ieee 802.3 clause 40.4.4 ensures that only one device performs the required crossover. 2.2.10 polarity correction if cabling has been incorrectly wired, the ar8035 automatically corrects polarity errors on the receive pairs in 1000 base-t, 100 base- tx and 10 base-te modes. 2.3 loopback modes 2.3.1 digital loopback digital loopback provides the ability to loop transmitted data back to the receiver using digital circuitry in the ar8035 device. figure 2- 1 shows a block diagram of a digital loopback. n 1000m loopback: write register 0x0 = 0x4140 to enable 1000m digital loopback. n 100m loopback: write register 0x0 = 0x6100 to enable 100m digital loopback. n 10m loopback: write register 0x0 = 0x4100 to enable 10m digital loopback. 2.3.2 external cable loopback external cable loopback loops tx to rx through a complete digital and analog path and an external cable, thus test ing all the digital data paths and all the analog circuits. figure 2-2 shows a block diagram of external cable loopback. 1. plug in an external loopback cable (1-3/2-6/ 4-7/5-8) 2. write debug register 0xb[15] = 0 to disable hibernate (power-saving mode) 3. write debug register 0x11[0] = 1 to enable external loopback 4. select wire speed, as follows: figure 2-1. digital loopback figure 2-2. external cable loopback mac/ switch rgmii phy digital phy afe mac/ switch rgmii/ sgmii phy digital phy afe rj-45
16 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 16 ? november 2011 company confidential n 1000m loopback: write register 0x0 = 0x8140 to set 1000m external loopback n 100m loopback: write register 0x0 = 0xa100 to set 100m external loopback n 10m loopback: write register 0x0 = 0x0x8100 to set 10m external loopback 5. when the cable in 1000m mode is re- plugged, need to write 0x0 = 0x8140 again to make the phy link. 2.3.3 remote phy loopback the remote loopback connects the mdi receive path to the mdi transmit path, near the rgmii interface, thus the remote link partner can detect the connectivity in the resulting loop. figure 2-3, below, shows the path of the remote loopback. figure 2-3 shows a block diagram of external cable loopback. n write mmd3 register 0x805a[0]= 1 to enable remote phy loopback. please note : the packets from link partner will still appear at rgmii interface when remote loopback is enabled. also, remote loopback is independent of phy auto-negotiation. 2.4 cable diagnostic test the cable diagnostic test (cdt) feature in the ar8035 device uses time domain reflectometry (tdr) to identify remote and local phy malfunctions, bad/marginal cable or patch cord segments, or connectors. some of the possible problems that can be diagnosed include opens, shorts, cable impedance mismatch, bad connectors, termination mismatch, and bad magnetics. the cdt can be performed when there is no link partner or when the link partner is auto-negotiating. 1. set register 0x16[9:8] to select mdi pair under test 2. write register 0x16[0]=1 to enable cdt 3. check register 0x1c[9:8] for fail status 4. check register 0x1c[7 :0] to get delta time. the distance between the fail point and phy is delta time *0.842 2.5 led interface the led interface can either be controlled by the phy or controlled manually, independent of the state of the phy. three status leds are available. these can be used to indicate operation speed, duplex mode, and link status. the leds can be programmed to different status functions from their default value. they can also be controlled directly from the mii register interface. the reference design schematics for the ar8035?s leds are shown figure 2-4 reference design schematic ? active low figure 2-5 reference design schematic ? active high led_act/led_1000 active states depend on power on strapping mode. figure 2-3. remote phy loopback mac/ switch rgmii/ sgmii phy digital phy afe rj-45 figure 2-4. reference design schematic active low figure 2-5. reference design schematic active high
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 17 company confidential november 2011 ? 17 when strapped high, active low. when strapped low, active high. led_10_100 depends on led_1000 power on strapping mode. so led_10_100 and led_1000 should have the same led design. note: notes: on = active; off = inactive table 2-4. led status symbol 10m link 10m active 100m link 100m active 1000m link 1000m active led_10_100 off off on on off off led_1000 off off off off on on led_act on blink on blink on blink
18 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 18 ? november 2011 company confidential 2.6 power supplies the ar8035 device requires only one external power supply: 3.3 v. inside the chip there is a 3.3v rail, 2.5v rail, 1.1v rail and a 1.8v/1.5v rail. ar8035 integrates a switch regulator which converts 3.3v to 1.1v at a high-efficiency for core power rail. (it is optional for an external regulator to provide this core voltage). the ar8035 integrates two on chip ldos which can support 2.5v; 1.5v/1.8v rgmii i/o voltage. also with 2.5v rgmii i/o voltage configuration ar8035 can work with a 3.3v mac rgmii interface ? because the input can bear 3.3v logic signal, and the output logic voh and vol can satisfy the 3.3v lvcmos/ lvttl requirement. the parameter details are in the electrical characteristics chapter. reference design for 2.5v rgmii voltage level is shown below: figure 2-6 shows the ar8035 reference design for a 2.5v rgmii voltage level. reference design for 1. 5/1.8v rgmii voltage level is shown below: figure 2-6. ar8035 reference design for a 2.5v rgmii voltage level arctic 2.5v rgmii vddio_reg lx vdd33 avddl avddl avddl avdd33 vddh_reg dvddl 4.7uh bead 10uf 0.1uf 0.1uf 0.1uf 1uf 0.1uf 10uf0.1uf 0.1uf 0.1uf 0.1uf 1uf 3.3v input bead
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 19 company confidential november 2011 ? 19 figure 2-7 shows the ar8035 reference design for a 1.5/1.8v rgmii voltage level. 2.7 management interface the ar8035 integrates an mdc/mdio management interface which is compliant with ieee802.3u clause 22. mdc is an input clock reference provided by the mac. mdio is the management data input/output bi-directional signal that runs synchronously to mdc. mdio is an od-gate, needs an external 1.5k pull-up resistor. definition of the management frame is shown below. figure 2-8 shows the ar8035 management frame fields. figure 2-7. ar8035 reference design for a 1.5/1.8v rgmii voltage level arctic 1.5/1.8v rgmii vddio_reg lx vdd33 avddl avddl avddl avdd33 vddh_reg dvddl 4.7uh bead 10uf 0.1uf 0.1uf 0.1uf 0.1uf 1uf 10uf0.1uf 0.1uf 0.1uf 0.1uf 1uf 3.3v input bead figure 2-8. ar8035 management frame fields
20 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 20 ? november 2011 company confidential 1. pre is a sequence of 32 contiguous logic one bits on mdio with 32 corresponding cycles on mdc to provide the phy with a pattern that it can use to establish synchronization. 2. st is start of frame 3. op is the operation code. the operation code for a read transaction is <10>, while the operation code for a write transaction is <01>. 4. phyad is 5 bits phy address. phy address of ar8035 is configured by power on strapping. there are three address bits can be configured in ar8035 which means 8 phys can be connected to the same management interface. each phy connected to the same bus line should have a unique phy address. the first phy address bit transmitted and received is the msb of the address. 5. the register address is five bits, allowing 32 individual registers to be addressed within each phy. the first register address bit transmitted and received is the msb of the address. 6. ta is 2 bits to avoid contention during a read operation. for a read operation, both the mac and phy shall remain in a high- impedance state for the first bit time. the phy shall drive a zero during the second bit time of the turnaround. during a write transaction, the mac must drive 10. 7. data is the 16 bits data from accessed register. msb is transmitted first. 8. idle is a high-impedance without driving state of the mdio. at least one clocked idle state is required between frames. there are three kinds of registers in ar8035. all can be accessed using the management frames. 1. ieee defined 32 mii registers. 2. atheros defined debug registers. 3. ieee defined mdio manageable device (mmd) register mii register can be access directly through the frame defined above. debug register access: 1. write the debug offset address to 0x1d 2. read/ write the data from/to 0x1e mmd register access: see detail in register description example: write 0x8000 to register 0 of mmd3 1. write 0x3 to register 0xd: 0xd=0x0003; (function= address; set the device address) 2. write 0x0 to register 0xe: 0xe=0x0; (set the register offset address) 3. write 0x4003 to register 0xd:0xd=0x4003; (function = data; keep the device address) 4. read register 0xe:0xe==(data from register 0x0 of mmd3) 5. write 0x8000 to register 0xe:0xe = 0x8000 (write 0x8000 to register 0x0 of mmd3) note: read operation please refers to process 1 ~ 4 2.8 atheros green ethos? 2.8.1 low power modes the ar8035 device supports the software power-down low power mode. the standard ieee power-down mode is entered by setting the power_down bit (bit [11]) of the register ?control? equal to one. in this mode, the ar8035 ignores all mac interface signals except the mdc/mdio. it does not respond to any activity on the cat 5 cable. the ar8035 cannot wake up on its own. it can only wake up by setting the power_down bit of the ?control? register to 0, or a hardware reset see table 4.1.1 on page 32 . 2.8.2 shorter cable power mode with atheros latest proprietary green ethos ? power saving technology, the ar8035 can attain an additional 25% power savings when a cable length is detected that is < 30m vs. standard power consumption for a 100m cat5 cable. the equals and additional 100mw power savings and less than 350mw total power for 1000base-t mode in a typical home application. 2.8.3 hibernation mode the ar8035 supports hibernation mode. when the cable is unplugged, the ar8035 will enter hibernation mode after about 10 seconds. the power consumption in this mode can go as low as 10mw only when compared to the normal mode of operation. when the cable is re-
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 21 company confidential november 2011 ? 21 connected, the ar8035 wakes up and normal functioning is restored. 2.9 ieee 802.3az and energy efficient ethernet ieee 802.3az provides a mechanism to greatly save the power consumption between data packets bursts. the link partners enter low power idle state by sending short refresh signals to maintain the link. there are two operating states, active state for normal data transfer, and low-power state between the data packet bursts. in the low-power state, phy shuts off most of the analog and digital blocks to reserve energy. due to the bursty traffic nature of ethernet, system will stay in low-power mode in the most of time, thus the power saving can be more than 90%. at the link start up, both link partners exchange information via auto negotiation to determine if both parties are capable of entering lpi mode. legacy ethernet products are supported, and this is made transparent to the user. 2.9.1 ieee 802.3az lpi mode ar8035 works in the following modes when 802.3 az feature is turned on: n active: the regular mode to transfer data n sleep: send special signal to inform remote link of entry into low-power state n quiet: no signal transmitted on media, most of the analog and digital blocks are turned off to reduce energy. n refresh: send periodically special training signal to maintain timing recovery and equalizer coefficients n wake: send special wake-up signal to remote link to inform of the entry back into active. figure 2-9 shows the 802.3az operating states for the ar8035. figure 2-9. operating states 802.3az lpi mode active active td quiet quiet quiet low-power refresh refresh sleep wake ts tq tr tw existing state used for data transmission. data packets or ipg/idle symbols are transmitted new state used during periods of no data transmission to allow system power reduction between data packet bursts operating states
22 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 22 ? november 2011 company confidential figure 2-10 shows the 802.3az operating power modes ? 802.3az for the ar8035. the ar8035 supports both 100base-tx eee and 1000base-t eee. 100base-tx eee allows asymmetrical operation, which allows each link partner to enter the lpi mode independent of the other partner. 1000base-t eee requires symmetrical operation, which means that both link partners must enter the lpi mode simultaneously. 2.10 atheros smarteee ar8035 smarteee is compatible with normal 802.3az standard. it helps legacy mac without eee ability to work as a complete eee power saving system. ar8035 smarteee will detect egress data flow, if there are no packets to transfer after a defined time which are configurable based on system design, it will enter eee mode. if there are packets need to transfer, ar8035 will wait typically 16.5us to wake up as 802.3az defined and send out data after the timer configuration in register. it provides a 2048*20bit buffer for egress data before waking up to ensure no packet loss. ar8035 default mode enables smart eee after power on or hardware reset. working in smarteee, ar8035 rx side will not generate mdi lpi pattern. so only normal packets and idle packets will appear on the rgmii interface. there is no tx lpi pattern at all if mac has no eee capability. lpi is generated inside phy according to smarteee mechanism. if the mac has eee capability, can write smarteee control register to bypass smarteee function. please note : 1. wait time before entering eee mode is in register mmd3 0x805c,0x805d[7:0]; 2. adjustable wait time before sending out data is in register mmd3 0x805b, to cooperate with link partner for special requirement. 2.11 wake on lan (wol) originally wake-on-lan (wol) was an ethernet networking standard that allowed a computer to be turned on (or woken up) by a network message for administrator attention, etc. however as part of the latest industry trend towards energy savings, wol gets wide interest to be adopted across networking systems as a mechanism to help to manage and regulate the total power consumed by the network. the ar8035 supports wake-on-lan (wol): n able to enter the sleep/isolate state (phy?s all tx bus (including clock) are in high-z state, but phy can still receive packets) by isolate bit in mii register configuration n consumes less than 50mw when in sleep/ isolate mode n supports automatic detection of magic packets (a specific frame containing anywhere within its payload: 6 bytes of ones (resulting in hexadecimal ff ff ff ff ff ff), followed by sixteen repetitions of the target computer's mac address) and notification via hardware interrupt. n supports exit from the sleep state, by register configuration figure 2-10. operating power modes 802.3az lpi mode active active quiet quiet quiet low-power active active refresh refresh sleep wake td ts tq tr tw
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 23 company confidential november 2011 ? 23 3. electrical characteristics 3.1 absolute maximum ratings table 3-1 summarizes the absolute maximum ratings and table 3-2 lists the recommended operating conditions for the ar8035. absolute maximum rating s are those values beyond which damage to the device can occur. functional oper ation under these conditions, or at any other condition beyond those indicated in the operational sections of this document, is not recommended. 3.2 recommended operating conditions note: external regulators are optional for supplying avddl/dvddl. for industrial version, external avddl/dvddl inputs must be within the range of 1. 2 v 5%. for commercial version, external avddl/ dvddl inputs must be within the range of 1.1 v-5% and 1.2 v+5%. note: the following condition must be satisfied: t jmax > t cmax + jt x p typical where: t jmax = maximum allowable temperature of the junction t cmax = maximum allowable case temperature table 3-1. absolute maximum rating symbol parameter max rating unit v dd33 3.3v analog supply voltage 3.8 v a vdd 1.1v analog supply voltage 1.6 v d vdd 1.1v digital core supply voltage 1.6 v t store storage temperature ?65 to 150 c hbm electrostatic discharge tolerance - human body model 2kv v mm machine model 200v v cdm charge device model 500v v table 3-2. recommended operating conditions symbol parameter min typ max unit vdd33/avdd33 3.3v supply voltage 3.14 3.3 3.47 v avddl/dvddl 1.1v digital core supply voltage 1.04 1.1 1.17 v t a ambient temperature for normal operation - commercial chip version 0?70 c t a ambient temperature for normal operation - industrial chip version -40 ? 85 c t j junction temperature -40 ? 125 c jt thermal dissipation coefficient ? 4 ? c/w
24 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 24 ? november 2011 company confidential jt = thermal dissipation coefficient p typical = typical power dissipation 3.3 rgmii characteristics table 3-3 shows the rgmii dc characteristics with 2.5/3.3v i/o supply. table 3-4 shows the rgmii dc characteristics with 1.8v i/o supply. table 3-5 shows the rgmii dc characteristics with 1.5v i/o supply. table 3-3. rgmii characteristics with 2.5v 3.3v supply symbol parameter min max unit i ih input high current ? 15 a i il input low current ?15 ? a v ih input high voltage 1.7 3.5 v v il input low voltage ? 0.7 v v oh output high voltage 2.4 2.8 v v ol output low voltage gnd ? 0.3 0.4 v table 3-4. rgmii characteristics with 1.8v supply symbol parameter min max unit v ih input high voltage 1.4 ? v v il input low voltage ? 0.4 v v oh output high voltage 1.5 ? v v ol output low voltage ? 0.3 v table 3-5. rgmii characteristics with 1.5v supply symbol parameter min max unit v ih input high voltage 1.2 ? v v il input low voltage ? 0.3 v v oh output high voltage 1.3 ? v v ol output low voltage ? 0.2 v
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 25 company confidential november 2011 ? 25 figure 3-1 shows the rgmii ac timing diagram ? no internal delay. table 3-6 shows the rgmii ac characteristics. figure 3-1. rgmii ac timing diagram no internal delay rx_clk, gtx_clk rx_dv, tx_en txd[3:0], rxd[3:0] rx_clk, gtx_clk tskewr tskewt table 3-6. rgmii ac characteristics symbol parameter min typ max unit t skewt data to clock output skew (at transmitter) -500 0 500 ps t skewr data to clock output skew (at receiver) 1 ? ? ns t cyc clock cycle duration 7.2 8.0 8.8 ns duty_g duty cycle for gigabit 45 50 55 % duty_t duty cycle for 10/100t 40 50 60 % t r /t f rise/fall time (20 - 80%) ? ? 0.75 ns
26 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 26 ? november 2011 company confidential figure 3-2 shows the rgmii ac timing diagram with internal delay added (default rgmii timing). table 3-7 shows the rgmii ac characteristics with delay added. 3.4 mdio characteristics mdio is od-gate, and can be pulled-up to 2.5/3.3v. table 3-8 shows the mdio dc characteristics. figure 3-2. rgmii ac timing diagram with internal delay added (default) gtx_clk txd[3:0], tx_en rxd[3:0], rx_dv rx_clk rxc with internal delay added tsetupt tsetupr tholdr tholdt table 3-7. rgmii ac characteristics with delay symbol parameter min typ max unit tsetupt data to clock output setup (at transmitter ? integrated delay) 1.65 2.0 2.2 ns tholdt clock to data output hold (at transmitter ? integrated delay) 1.65 2.0 2.2 ns tsetupr data to clock input setup setup (at receiver ? integrated delay) 1.0 2.0 ns tholdr data to clock output setup setup (at receiver ? integrated delay) 1.0 2.0 ns table 3-8. mdio characteristics symbol parameter min max unit i ih input high current ? 0.4 ma i il input low current 0.4 ? ma v oh output high voltage 2.4 ? v v ol output low voltage ? 0.4 v v ih input high voltage 2.0 ? v v il input low voltage ? 0.8 v
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 27 company confidential november 2011 ? 27 table 3-9 shows the mdio ac characteristics. 3.5 xtal/osc characteristics table 3-9. mdio ac characteristics symbol parameter min typ max unit tmdc mdc period 40 ns tmdcl mdc low period 16 ns tmdch mdc high period 16 ns tmdsu mdio to mdc rising setup time 10 ns tmdhold mdio to mdc rising hold time 10 ns tmdelay mdc to mdio output delay 0 4 ns table 3-10. xtal/osc characteristics symbol parameter min typ max unit t_xi_per xi/osci cl ock period 40.0 - 50ppm 40.0 40.0 + 50ppm ns t_xi_hi xi/osci cl ock high 14 20.0 ns t_xi_lo xi/osci clock low 14 20.0 ns t_xi_rise xi/osci clock rise time, vil (max) to vih (min) 4ns t_xi_fall xi/osci cl ock fall time, vil (max) to vih (min) 4ns v_ih_xi the xi input high level 0.8 1.2 1.5 v v_il_xi the xi input low level voltage - 0.3 0 0.15 v cin load capacitance 1 2 pf jitter_rms period broadband rms jitter 15 ps jitter_pk-pk period broadband pk-pk jitter 200 ps table 3-11. xtal/osc selection symbol min typ max unit frequency -50ppm 20, 50, 62.5, 125 +50ppm mhz output high voltage 2.3 2.62 2.8 v output low voltage gnd-0.3 0 0.4 v jitterrms 15 ps jitterpk-pk 125 ps
28 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 28 ? november 2011 company confidential note: clk_25m default outputs 25mhz, can be configured to 50mhz, 62.5mhz, or 125mhz by register mmd7 8016[4:3]. note: the jitter result is broadband period jitter with 100000 samples. 3.6 power pin consumption note: data for components selection and layout guide table 3-12. power pin consumptions symbol voltage range current avddl 1.1v 5% 50.8 ma dvddl 1.1v 5% 113.7 ma avdd33 3.3v 5% 63.8 ma vddio_reg connect vddh_reg 2.5v 20.9 ma
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 29 company confidential november 2011 ? 29 3.7 typical power consumption parameters the following conditions apply to the typical characteristics unless otherwise specified: vcc = 3.3v (1.1v switching regulator integrated. 1.8v rgmii power included). note: power consumption test results are based on atheros demo board. table 3-13. typical power consumptions symbol condition total current (ma) led consumption (ma) total power consumption w/o led (mw) p ldps link down, power saving mode 3.0 0 9.9 p pwd power down mode 2.5 0 8.25 p 1000f 1000base full duplex 119 2.7 392.7 p 1000f 1000base idle 109 4 359.5 p 100f 100base full duplex 33.9 3.5 111.9 p 100f 100base idle 32.6 4 107.6 p 10f 10base-te full duplex 31.5 1 104.0 p 10idle 10base-te idle 9.4 1.5 31.0 802.3az enabled p lpi 1000m idle 20.0 4.0 66.0 p lpi 100m idle 14.7 4.0 48.5 atheros proprietary green ethos?power savigns per cable length p 1000f 20m 1000base full duplex 20m cable 92.0 2.7 303.6 p 1000f 20m 1000base idle 20m cable 85.0 4 280.5 p 1000f 100m 1000base full duplex 100m cable 119.0 2.7 392.7 p 1000f 100m 1000base idle 100m cable 109 4 359.7 p 1000f 140m 1000base full duplex 140m cable 137.0 2.7 452.1 p 1000f 140m 1000base idle 140m cable 128.0 4 422.4
30 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 30 ? november 2011 company confidential 3.8 power-on sequence, reset and clock 3.8.1 power-on sequence the ar8035 only needs a single 3.3v power supply in put. the 1.1v core and 2.5v, 1.8v/1.5v voltages are generated by ar8035's internal regulators. so the ar8035?s power-on sequence to establish the power rails stability is met internally. 3.8.2 reset and clock timing the ar8035 hardware reset needs the clock to take effect. input clock including the crystal and external input clock should be stable for at least 1ms before reset can be deasserted. for chip reliability, an external clock must be input after the power-on sequence. figure 3-3 shows the reset timing diagram. when using crystal, the clock is generated internally after power is stable. for a reliable power on reset, suggest to keep asserting the reset low long enough (10ms) to ensure the clock is stable and clock-to-reset 1ms requirement is satisfied. figure 3-3. reset timing diagram >0ms >/= 1ms 3.3v xi clock reset >/= 1ms
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 31 company confidential november 2011 ? 31 4. register descriptions table 4-1 shows the reset types used in this document. 4.1 register summary table 4-2 summarizes the registers for the ar8035. table 4-1. reset types type description lh register field with la tching high function. if status is high, then the register is set to one and remains set until a read operation is performed through the management interface or a reset occurs. ll register field with latching low function. if status is low, then the register is cleared to a zero and remains cleared until a read operation is performed through the management interface or a reset occurs. retain value written to a register field takes effect without a software reset. sc self-clear. writing a one to this register causes the desired function to execute immediately, and the register field clears to zero when the function is complete. update the value written to the register field does not take effect until a software reset is executed. the value can still be read after it is written. table 4-1. reset types type description table 4-2. register summary offset register 0x00 control 0x01 status 0x02 phy identifier [18:3] 0x03 phy identifier [19:24] 0x04 auto-negotiation advertisement 0x05 link partner ability (base page) 0x06 auto-negotiation expansion 0x07 next page transmit 0x08 link partner next page 0x09 1000 base-t control 0x0a 1000 base-t status 0x0b reserved 0x0c reserved 0x0d mmd access control 0x0e mmd access control data 0x0f extended status 0x10 function control 0x11 phy-specific status 0x12 interrupt enable 0x13 interrupt status 0x14 smart speed 0x15 reserved
32 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 32 ? november 2011 company confidential 4.1.1 control offset: 0x00 mode: read/write hardware reset: 0x3100 software reset: see field descriptions 0x16 cable defect tester control 0x17 reserved 0x18 led control 0x19 reserved 0x1a reserved 0x1b reserved 0x1c cable defect tester status 0x1d debug port address offset 0x1e debug port data 0x1f reserved table 4-2. register summary offset register bit name sw reset description 15 reset sc phy software reset 0 normal operation 1phy reset writing a 1 to this bit causes immediate phy reset. once the operation is done, this bit clears to 0 automatically. 14 loopback 0 when loopback is active, the transmitter data on txd loops back to rxd internally. the link breaks when loopback is enabled. 0 disable loopback 1 enable loopback 13 speed_selection (lsb) retain force_speed = {register 0.6, this bit}: 2?b00 = 10mbps 2?b01 = 100mbps 2?b10 = 1000mbps 2?b11 = reserved 12 auto_ negotiation retain 0 disable auto-negotiation process 1 enable auto-negotiation process 11 power_down 0 when the port is switched from power down to normal operation, software reset and restart auto-negotiation are performed even when bit reset (0.15)and restart au to-negotiation (0.9) are not set by the user. ieee power down shuts down the chip except for the mac interface if 16.3 is set to 1. if 16.3 is set to 0, then the mac interface also shuts down. power-down has no effect on the 125clk output if 16.4 is set to 0. 0 normal operation 1power-down
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 33 company confidential november 2011 ? 33 10 isolate 0 the rgmii/rmiioutput pins are tri-statedwhen thei bit is set to 1. the rgmii/rmii in puts are ignored. 1 = isolate 0 = normal operation 9restart_auto_ negotiation sc auto-negotiation automatically restarts after hardware or software reset regardless of whether or not this bit is set. 0 normal operation 1 restart auto-negotiation process 8 duplex mode retain . 0 half-duplex 1 full-duplex 7collision test 0 0 disable col signal test 1 enable col signal test 6 speed selection (msb) retain see description in bit [ "13" ] 5:0 res 00000 reserved. always set to 00000. bit name sw reset description
34 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 34 ? november 2011 company confidential 4.1.2 status offset: 0x01 mode: read-only hardware reset: 0x7949 software reset: see field descriptions bit name sw reset description 15 100base-t4 0 100 base-t4 this protocol is not available 0 phy not able to perform 100 base-t4 14 100base-x full-duplex 1 capable of 100-tx full duplex operation 13 100base-x half-duplex 1 capable of 100-tx half duplex operation 12 10 mbps full- duplex 1 capable of 10 base-t full duplex operation 11 10 mbs half-duplex 1 capable of 10 base-t half duplex operation 10 100base-t2 full-duplex 0 not able to perform 100 base-t2 9 100base-t2 half-duplex 0 not able to perform 100 base-t2 8 extended status 1 extended status information in the register ?extended status? on page 43 7 reserved 0 always 0 6 mf preamble suppression 1 phy accepts management fram es with preamble suppressed 5auto- negotiation complete 0 0 auto negotiation process not complete 1 auto negotiation process complete 4 remote fault 0 this bit cl ears after read ?sc?. 0 remote fault condition not detected. 1 remote fault condition detected 3auto- negotiation ability 1 phy able to perform auto negotiation 2 link status 0 indicates whet her the link was lost sinc e the last read. for the current link status, read link_real_time (bit [10]) of the register ?phy-specific status? on page 44 . latching low function. 0 link is down 1link is up 1 jabber detect 0 this bit cl ears after read ?sc?. 0 jabber condition not detected 1 jabber condition detected 0 extended capability 1 extended register capabilities
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 35 company confidential november 2011 ? 35 4.1.3 phy identifier [18:3] offset: 0x02 mode: read-only hardware reset: 0x004d software reset: 0x004d 4.1.4 phy identifier [19:24] offset: 0x03 mode: read-only hardware reset: 0xd072 software reset: 0xd072 4.1.5 auto-negotiation advertisement offset: 0x04 mode: read/write hardware reset: 0x1de1 software reset: see field descriptions bit name description 15:0 unique identifier bit organizationally uniq ue identifier bits [18:3]. always 16?h004d bit name description 15:0 oui lsb model revision organizationally unique identifi er bits [19:24]. always 16?hd072 bit name sw reset description 15 next_page retain the value of this bit will be updated immediately after writing this register. but the value written to th is bit does not takes effect until any one of the following occurs: o software reset is asserted (register 0.15) o restart auto-negotia tion is asserted (register 0.9) o power down (register 0.11) transitions from power down to normal operation o link goes down if 1000 base-t is advertised then the required next pages are automatical ly transmitted. register 4.15 should be set to 0 if no additional next pages are needed. 0 not advertised 1advertise 14 ack 0 must be set to 0 13 remote fault retain write a 1 to set remote fault 12 xnp_able 1 extended next page enable control bi: 1 = local device supports transmission of extended next pages; 0 = local device does not support transmission of extended next pages. 11 asymmetric pause retain upon hardware reset , this bit depends on asym_pause_pad. the value of this bit will be updated immediately after writing this register. but the value written to th is bit does not takes effect until any one of the following occurs: o software reset is asserted (register 0.15) o restart auto-negotia tion is asserted (register 0.9) o power down (register 0.11) transitions from power down to normal operation o link goes down 1 = asymmetric pause 0 = no asymmetric pause
36 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 36 ? november 2011 company confidential 10 pause retain the value of this bit will be updated immediately after writing this register. but the value written to th is bit does not takes effect until any one of the following occurs: o software reset is asserted (register 0.15) o restart auto-negotia tion is asserted (register 0.9) o power down (register 0.11) transitions from power down to normal operation o link goes down 1 = mac pause implemented 0 = mac pause not implemented 9 100base-t4 0 not able to perform 100 base-t4 8 100base-tx full duplex retain the value of this bit will be updated immediately after writing this register. but the value written to th is bit does not takes effect until any one of the following occurs: o software reset is asserted (register 0.15) o restart auto-negotia tion is asserted (register 0.9) o power down (register 0.11) transitions from power down to normal operation o link goes down 1 = advertise 0 = not advertised 7 100base-tx half duplex retain the value of this bit will be updated immediately after writing this register. but the value written to th is bit does not takes effect until any one of the following occurs: o software reset is asserted (register 0.15) o restart auto-negotia tion is asserted (register 0.9) o power down (register 0.11) transitions from power down to normal operation o link goes down 1 = advertise 0 = not advertised 6 10base-tx full duplex retain the value of this bit will be updated immediately after writing this register. but the value written to th is bit does not takes effect until any one of the following occurs: o software reset is asserted (register 0.15) o restart auto-negotia tion is asserted (register 0.9) o power down (register 0.11) transitions from power down to normal operation o link goes down 1 = advertise 0 = not advertised 5 10base-tx half duplex retain the value of this bit will be updated immediately after writing this register. but the value written to th is bit does not takes effect until any one of the following occurs: o software reset is asserted (register 0.15) o restart auto-negotia tion is asserted (register 0.9) o power down (register 0.11) transitions from power down to normal operation o link goes down 1 = advertise 0 = not advertised 4:0 selector field 00001 selector field mode 00001 802.3 bit name sw reset description
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 37 company confidential november 2011 ? 37 4.1.6 link partner ability (base page) offset: 0x05 mode: read-only hardware reset: 0 software reset: 0 bit name description 15 next page received code word bit [15] 0 link partner not capable of next page 1 link partner capable of next page 14 ack acknowledge; received code word bit [14] 0 link partner does not have next page ability 1 link partner received link code word 13 remote fault received code word bit [13] 0 link partner has not detected remote fault 1 link partner detected remote fault 12 reserved technology ability field received code word bit [12] 11 asymmetric pause received code word bit [11] 0 link partner does not request asymmetric pause 1 link partner requests asymmetric pause 10 pause received code word bit [10] 0 link partner is not capable of pause operation 1 link partner is capable of pause operation 9 100base-t4 received code word bit [9] 0 link partner is not 100 base-t4 capable 1 link partner is 100 base-t4 capable 8 100base-tx full duplex received code word bit [8] 0 link partner is not 100 base-tx full-duplex capable 1 link partner is 100 base-tx full-duplex capable 7 100base-tx half duplex received code word bit [7] 0 link partner is not 100 ba se-tx half-duplex capable 1 link partner is 100 base-tx half-duplex capable 6 10base-tx full duplex received code word bit [6] 0 link partner is not 10 base-t full-duplex capable 1 link partner is 10 base-t full-duplex capable 5 10base-tx half duplex received code word bit [5] 0 link partner is not 10 base-t half-duplex capable 1 link partner is 10 base -t half-duplex capable 4:0 selector field received code word bit [4:0]
38 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 38 ? november 2011 company confidential 4.1.7 auto-negotiation expansion offset: 0x06 mode: read-only hardware reset: 0x0004 software reset: decided by the phy inner state 4.1.8 next page transmit offset: 0x07 mode: read/write reset: see field descriptions bit name description 15:5 res reserved. must be set to 0. 4 parallel detection fault software resets this bit to 0; clear after read 0 no fault has been detected 1 a fault has been detected 3 link partner next page able software resets this bit to 0; clear after read 0 link partner is not next page capable 1 link partner is next page capable 2 local next page able 0 local device is not next page capable 1 local device is next page able 1 page received on software reset, this bit value is reserved; lh; cleared after a read. 0 no new page has been received 1 a new page has been received 0 link partner auto- negotiation able software reset to 0. 0 link partner is not auto-negotiation capable 1 link partner is auto-negotiation capable bit name reset description 15 next page 0 transmit code word bit [15] 14 res 0 transmit code word bit [14] 13 message page mode 1 transmit code word bit [13] 12 ack2 0 transmit code word bit [12] 11 toggle 1 transmit code word bit [11] 10:0 message/ unformatted field 0x001 transmit code word bits [10:0]
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 39 company confidential november 2011 ? 39 4.1.9 link partner next page offset: 0x08 mode: read-only hardware reset: 0 software reset: 0 4.1.10 1000 base-t control offset: 0x09 mode: read/write hardware reset: 0x0200 software reset: see field descriptions bit name description 15 next page receive code word bit [15] 14 ack receive code word bit [14] 13 message page mode receive code word bit [13] 12 ack2 receive code word bit [12] 11 toggle receive code word bit [11] 10:0 message/ unformatted field receive code word bits [10:0] bit name sw reset description 15:13 test mode retain hardware reset or software reset (see reset (bit [15]) of the register ?function control? on page 43 ) should be issued to ensure normal operation after exiting the test mode. 000 normal mode 001 test mode 1: transmit waveform test 010 test mode 2: transmit jitter test (master mode) 011 test mode 3: transmit jitter test (slave mode) 100 test mode 4: transmit distortion test 101, 110, 111 reserved 12 master/slave manual configuration enable retain the value of this bit will be updated immediately after writing this register. but the value wr itten to this bit does not takes effect until any one of the following occurs: o software reset is asserted (register 0.15) o restart auto-negotiat ion is asserted (register 0.9) o power down (register 0.11) transi tions from power down to normal operation o link goes down 1 = manual master/slave configuration 0 = automatic master/slave configuration 0 automatic master/slave configuration 1 manual master/slave configuration
40 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 40 ? november 2011 company confidential 11 master/slave configuration retain the value of this bit will be updated immediately after writing this register. but the value wr itten to this bit does not takes effect until any one of the following occurs: o software reset is asserted (register 0.15) o restart auto-negotiat ion is asserted (register 0.9) o power down (register 0.11) transiti ons from power down to normal operation o link goes down register 9.11 is ignored if register 9.12 is equal to 0. 1 = manual co nfigure as master 0 = manual configure as slave 0 manual configure as slave 1 manual configure as master 10 port type retain the value of this bit will be updated immediately after writing this register. but the value wr itten to this bit does not takes effect until any one of the following occurs: o software reset is asserted (register 0.15) o restart auto-negotiat ion is asserted (register 0.9) o power down (register 0.11) transiti ons from power down to normal operation o link goes down register 9.10 is ignored if register 9.12 is equal to 1. 0 prefer single port device (slave) 1 prefer multi-port device (master) 9 1000base-t full duplex retain the value of this bit will be updated immediately after writing this register. but the value wr itten to this bit does not takes effect until any one of the following occurs: o software reset is asserted (register 0.15) o restart auto-negotiat ion is asserted (register 0.9) o power down (register 0.11) transiti ons from power down to normal operation o link goes down 1 = ad vertise 0 = not advertised when giga_dis_qual(register20.8) is high , this bit is forced to be low. 8 1000base-t half-duplex retain the value of this bit will be updated immediately after writing this register. but the value wr itten to this bit does not takes effect until any one of the following occurs: o software reset is asserted (register 0.15) o restart auto-negotiat ion is asserted (register 0.9) o power down (register 0.11) transiti ons from power down to normal operation o link goes down 1 = advertise 0 = not advertised note: the default setting is no 1000 base t/half duplex advertised when giga_dis_qual(register20.8) is high , this bit is forced to be low. 7:0 res 0 reserved bit name sw reset description
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 41 company confidential november 2011 ? 41 4.1.11 1000 base-t status offset: 0x0a mode: read-only hardware reset: 0 software reset: 0 note: contents of this register clear after a read operation has occurred. bit name description 15 master/slave configuration fault this register bit will clear on read 0 no fault detected 1 master/slave configuration fault detected 14 master/slave configuration resolution this register bit is not valid until page_received (bit [1]) of the register ?auto-negotiation expansion? on page 38 is 1 0 local phy configuration resolved to slave 1 local phy configuration resolved to master 13 local receiver status 0 local receiver not ok 1 local receiver ok 12 remote receiver status 0 remote receiver not ok 1 remote receiver ok 11 link partner 1000base-t full duplex capability this register bit is not valid until page_received (bit [1]) of the register ?auto-negotiation expansion? on page 38 is 1 0 link partner is not capable of 1000 base-t half duplex 1 link partner is capable of 1000 base-t half duplex 10 link partner 1000base-t half duplex capability this register bit is not valid until page_received (bit [1]) of the register ?auto-negotiation expansion? on page 38 is 1 0 link partner is not capable of 1000 base-t full duplex 1 link partner is capable of 1000 base-t full duplex 9:8 res reserved. 7:0 idle error count reports the idle error count since the last time this register was read. the counter stops at 11111111 and does not roll over. these bits clear on a read.
42 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 42 ? november 2011 company confidential 4.1.12 mmd access address register offset: 0x0e mode: read-only hardware reset: 0 software reset: 0 4.1.13 mmd access control register offset: 0x0d mode: read-only note: contents of this register clear after a read operation has occurred. bit name type description 15:0 address data mode r/w if register13.15: 14=00, mmd devad's address register. otherwise, mmd devad's data register as indicated by the contents of its address register hw rst 00 sw rst retain bit name type description 15:14 function mode r/w 00=address 01=data,no post increment 10=data,post increment on reads and writes 11=data,post increment on writes only; hw rst 00 sw rst retain 13:5 reserved mode ro hw rst 0 sw rst 0 4:0 devad mode r/w device address hw rst 00 sw rst update
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 43 company confidential november 2011 ? 43 4.1.14 extended status offset: 0x0f mode: read-only hardware reset: 0x2000 software reset: 0 4.1.15 function control offset: 0x10 mode: read/write hardware reset: 0x0862 software reset: see field descriptions bit name description 15 1000base-x full duplex phy not able to perform 1000 base-x full duplex 14 1000base-x half duplex phy not able to perform 1000 base-x half duplex 13 1000base-t full-duplex phy able to perform 1000 base-t full duplex 12 1000base-t half-duplex phy not able to perform 1000 base-t half duplex 11:0 res reserved bit name sw reset description 15:12 reserved 11 assert_crs_on_ transmit retain this bit has effect in 10b t half-duplex mode and 100bt mode: 0never assert on transmit 1 assert on transmit 10 reserved 9:7 reserved 6:5 mdi_crossover_ mode update changes to these bits are disru ptive to the normal operation; therefore any changes to this register must be followed by a software reset to take effect. 00 manual mdi configuration 01 manual mdix configuration 10 reserved 11 enable automatic crossover for all modes
44 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 44 ? november 2011 company confidential 4.1.16 phy-specific status offset: 0x11 mode: read-only hardware reset: 0x0010 software reset: 0 4:3 res 0 reserved 2 sqe_test retain sqe test is automatically disabled in full-duplex mode regardless of the state of this bit 0 sqe test disabled 1 sqe test enabled 1polarity_ reversal retain if polarity is disabled, then the polarity is forced to be normal in 10 base-t 0 polarity reversal enabled 1 polarity reversal disabled 0 disable_jabber retain 0 enable jabber function 1 disable jabber function bit name sw reset description bit name description 15:14 speed valid only after resolved bit [11] of this register = 1. the resolved bit is set when auto-negotiation is completed or auto-negotiation is disabled. 00 10 mbps 01 100 mbps 10 1000 mbps 11 reserved 13 duplex valid only after resolved bit [11] of th is register = 1. the resolved bit is set when auto-negotiation is completed or auto-negotiation is disabled. 0 half-duplex 1 full-duplex 12 page_received (real-time) 0page not received 1 page received 11 speed_duplex_ resolved when auto-negotiation is not enabled, this bit = 1 for force speed 0 not resolved 1resolved 10 link (real-time) 0 link down 1link up 9:7 res reserved. always set to 0. 6 mdi_crossover_ status valid only after resolved bit [11] of this register = 1. the resolved bit is set when auto-negotiation is completed or auto-negoti ation is disabled. this bit is 0 or 1 depending on what is written to bits [6:5] of the register ?function control? on page 43 in manual configuration mode. ?function control? bits [6:5] are updated with software reset. 0mdi 1mdix 5smartspeed_ downgrade 0 smartspeed downgrade does not occur 1 smartspeed downgrade occurs
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 45 company confidential november 2011 ? 45 4.1.17 interrupt enable offset: 0x12 mode: read/write hardware reset: 0 software reset: see field descriptions 4 reserved 3transmit_pause _enabled valid only after resolved bit [11] of this register = 1. the resolved bit is set when auto-negotiation is completed or disa bled. a reflection of the mac pause resolution. 0 transmit pause disabled 1 transmit pause enabled 2receive_ pause_enabled a reflection of the mac pause resolution . this status bit is valid only after resolved bit [11] of this register = 1. th e resolved bit is set when auto-negotiation is completed or disabled. 0 receive pause disabled 1 receive pause enabled 1polarity (real-time) 0normal 1 reversed 0 jabber (real-time) 0 no jabber 1 jabber bit name description bit name sw reset description 15 auto-negotiation error interrupt enable retain 0 interrupt disable 1 interrupt enable 14 speed changed interrupt enable retain 0 interrupt disable 1 interrupt enable 13 duplex changed interrupt enable retain 0 interrupt disable 1 interrupt enable 12 page received interrupt enable retain 0 interrupt disable 1 interrupt enable 11 link fail interrupt retain 0 interrupt disable 1 interrupt enable 10 link success interrupt retain 0 interrupt disable 1 interrupt enable 9 reserved 8 reserved 7 reserved
46 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 46 ? november 2011 company confidential 4.1.18 interrupt status offset: 0x13 mode: read-only hardware reset: 0 note: all bits clear on read. 6 reserved 5 wirespeed- downgrade interrupt retain 0 interrupt disable 1 interrupt enable 4 reserved 3:2 res 0 reserved. always set to 00. 1 polarity changed interrupt enable retain 0 interrupt disable 1 interrupt enable 0 wake on lan interrupt enable 0 0 interrupt disable 1 interrupt enable bit name sw reset description bit name description 15 auto _negotiation_ error an error is said to occur if master/slave does not resolve, parallel detect fault, no common hcd, or link does not come up after negotiation is completed. 0 no auto-negotiation error 1 auto-negotiation error 14 speed_changed 0 speed not changed 1 speed changed 13 duplex_ changed 0 duplex not changed 1 duplex changed 12 page_received 0 page not received 1 page received 11 link_fail _interupt 0 1 = link down happened. 1 0 = link down not happened 10 link_sucess_int erupt 0 1 = link up happened. 1 0 = link up not happened 9:6 reserved 0 no symbol error 1symbol error 5 wirespeed_dow ngrade _interrupt 0 no smartspeed interrupt detected 1 smartspeed interrupt detected
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 47 company confidential november 2011 ? 47 4.1.19 smart speed offset: 0x14 mode: read/write hardware reset: 0x82c software reset: see field descriptions 4.1.20 cable diagnostic tester control offset: 0x16 mode: read/write hardware reset: 04e8 software reset: retain 4:2 reserved 0 1 1polarity_ changed 0 polarity not changed 1 polarity changed 0 int_wol_ptp 0 no wake-on-lan packet is received 1 wake-on-lan packet is received bit name description bit name reset description 15:6 res 0 reserved. must be set to 00001000. 5 smartspeed_en 1 the default value is one; if this bit is set to one and cable inhibits completion of the training phase, then after a few failed attempts, the device automatically adjusts the highest ability to the next lower speed: from 1000 to 100 to 10. 4:2 smartspeed_retry_limit 011 the default valu e is three; if set to three, then the device attempts five times before adjusting; the number of attempts can be changed through setting these bits. 000 2 retries 001 3 retries 010 4 retries 011 5 retries (default) 100 6 retries 101 7 retries 110 8 retries 111 9 retries 1 bypass_smartspeed_timer 0 0 the stable link condition is determined 2.5 seconds after the link is established (default) 1 the stable link condition is determined as soon as the link is established 0 reserved 0 reserved. must be set to 0.
48 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 48 ? november 2011 company confidential 4.1.21 led control offset: 0x018 bit name description 15:10 res reserved 9:8 mdi_pair_ select cable diagnostic tester (cdt) control registers use the cable defect tester control register s to select which mdi pair is shown in the register ?cable defect tester status? on page 49 . 00 mdi[0] pair 01 mdi[1] pair 10 mdi[2] pair 11 mdi[3] pair 7:1 res reserved 0 enable_test when set, hardware automatically disable this bit when cdt is done 0 disable cdt test 1enable cdt test bit name type description 15 reserved mode r/w hw rst. 0 sw rst retain 14:12 led on time mode r/w 000 = 5 ms 001 = 10ms 010 = 21 ms 011 = 42ms 100 = 84 ms 101 = 168ms 110 to 111 = 42ms hw rst. 011 sw rst retain 11 reserved mode r/w always 0 hw rst. 0 sw rst retain 10:8 led off time mode r/w 000 = 21 ms 001 = 42 ms 010 = 84 ms 011 =168 ms 100 =330 ms 101 = 670 ms 110 to 111 = 168ms hw rst. 010 sw rst retain 7:0 reserved mode r/w hw rst. 0 sw rst retain
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 49 company confidential november 2011 ? 49 4.1.22 cable defect tester status offset: 0x1c mode: read-only hardware reset: 0200 software reset: retain 4.1.23 debug port address offset offset: 0x1d mode: read/write hardware reset: 0 software reset: 0 4.1.24 debug port data offset: 0x1e mode: read/write hardware reset: 0x82ee software reset: 0x82ee bit name description 15:10 res reserved 9:8 status the content of this register applies to the cable pair selected in the register ?cable diagnostic tester control? on page 47 . 00 valid test, normal cable (n o short or open in cable) 01 valid test, short in cable (impedance < 33 ) 10 valid test, open in cable (impedance > 333 ) 11 test fail 7:0 delta_time delta time to indicate distance bit name description 15:6 res reserved 5:0 address_offset address index to access the debug registers bit name description 15:0 data data contents of the debug registers as addressed by the ?debug port address offset? register
50 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 50 ? november 2011 company confidential 4.2 debug register descriptions table 4-3 summarizes the debug registers for the ar8035. 4.2.1 rgmii rx clock delay control offset: 0x00 4.2.2 rgmii tx clock delay control offset: 0x05 table 4-3. offset register 0x00 debug register 0 0x05 debug register 5 0x10 100 base-tx test mode select 0x11 debug register 11 0x12 test configuration for 10 base-t bit name type description 15 sel_clk125m_dsp mode r/w control bit fo r rgmii interface rx clock delay: 1 = rgmii rx clock delay enable 0 = rgmii rx clock delay disable hw rst. 1 sw rst. 1 14:0 reserved mode ro hw rst. 2ee sw rst. 2ee bit name type description 15:9 reserved mode r/w hw rst. 1 sw rst. 1 8 rgmii_tx_clk_dly mode r/w rgmii tx clock delay control bit: 1 = rgmii tx clock delay enable 0 = rgmii tx clock delay disable. hw rst. 0 sw rst. retain 7:0 reserved mode ro hw rst. 2ee sw rst. 2ee
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 51 company confidential november 2011 ? 51 4.2.3 hibernation control and rgmii gtx clock delay register offset: 0x0b bit name type description 15 ps_hib_en mode r/w power hibernate control bit; 1: hibernate enable 0: hibernate disable hw rst. 1 sw rst. retain 14:13 reseved mode ro hw rst. 01 sw rst. 01 12 hib_pulse_sw mode r/w 1: wh en hibernate, phy sends nlp pulse and detects signal from cables. 0: when hibernate, phy doesn't send nlp pulse ,just detects signal from cables. hw rst. 1 sw rst. retain 11:7 reseved mode ro hw rst. 11000 sw rst. 11000 6:5 gtx_dly_val mode r/w select the delay of gtx_clk. 00:0.25ns 01:1.3ns 10:2.4ns 11:3.4ns hw rst. 2?b10 sw rst. retain 4:0 reseved mode ro hw rst. 0 sw rst. 0
52 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 52 ? november 2011 company confidential 4.2.4 100base-tx test mode select offset: 0x10 4.2.5 1000bt external loopback configure offset: 0x11 bit name type description 15:8 reserved mode ro always 0. hw rst. 0 sw rst. 0 7 jitter_test mode r/w 100bt jitter test hw rst. 0 sw rst. retain 6 os_test mode ro 100bt over shoot test hw rst. 0 sw rst. 0 5 dcd_test mode r/w 100bt dcd test hw rst. 0 sw rst. retain 4:0 reserved mode ro hw rst. 0 sw rst. 0 bit name type description 15:1 reserved mode ro hw rst. 3aa9 sw rst. 3aa9 0 ext_lpbk mode ro 1: enable the phy's ex ternal loopback, namely channel 0<- > channel 1, channel 2 <-> channel 3. hw rst. 0 sw rst. 0
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 53 company confidential november 2011 ? 53 4.2.6 rgmii_mode; test configuration for 10bt offset: 0x12 4.2.7 mmd3 (mdio manageable device address 3 for pcs) bit name type description 15:6 reserved mode ro hw rst. 0 sw rst. 0 5 test_mode[2] mode ro the bit2 of test_mode hw rst. 0 sw rst. 0 4 reserved mode ro hw rst. 0 sw rst. 0 3 reserved mode ro hw rst. 1 sw rst. 1 2 reserved mode ro hw rst. 1 sw rst. 1 1:0 test_mode[1:0] mode ro [001]: packet with all ones, 10mhz sine wave, for harmonic test. [010]: pseudo random, for tp_idle/jitter/differential vo l t a g e t e s t . [011]: normal link pulse only, [100]: 5mhz sin wave. others: normal mode. hw rst. 0 sw rst. 0 offset register description 0pcs control register 1pcs status register
54 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 54 ? november 2011 company confidential 4.2.8 mmd7 (mdio manageable device address 7 for auto-negotiation) 4.3 mdio interface register 4.3.1 pcs control 1 device address = 3 offset: 0x0 (hex) 20 eee capability 22 eee wake error counter offset register description offset register description 0an control 1an status 22 an xnp transmit 23 an xnp transmit1 24 an xnp transmit2 25 an xnp ability 26 an xnp ability1 27 an xnp ability2 60 eee advertisement 61 eee lp advertisement 32768 eee ability auto- negotiation result
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 55 company confidential november 2011 ? 55 bit name description 15 pcs_rst mode r/w reset bit, self clear. when write this bit 1 : 1, reset the registers(not vender specific) in mmd3/ mmd7. 2, cause software reset in mii register0 bit15. hw rst. 0 sw rst. 0 14:11 reserved mode ro always 0. hw rst. 0 sw rst. 0 10 clock_stoppable mod e r/w not implemented. hw rst. 0 sw rst. retain 9.0 reserved mode ro always 0. hw rst. 0 sw rst. 0
56 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 56 ? november 2011 company confidential 4.3.2 pcs status 1 device address = 3 offset: 0x1 (hex) bit name description 15:12 reserved mode ro always 0. hw rst. 0 sw rst. 0 11 tx lp idle received mode r/w when read as 1, it indicates that the transmit pcs has received low power idle signaling one or more times since the register was last read. latch high. hw rst. 0 sw rst. 0 10 rx lp idle received mode r/w when read as 1, it indicates that the recive pcs has received low power idle signaling one or more times since the register was last read. lach high. hw rst. 0 sw rst. 0 9 tx lp idle indication mode r/w when read as 1, it indicates that the transmit pcs is currently receiving low power idle signals. hw rst. 0 sw rst. 0 8 rx lp idle indication mode r/w when read as 1, it indicates that the receive pcs is currently receiving low power idle signals. hw rst. 0 sw rst. 0 7:0 reserved mode ro always 0. hw rst. 0 sw rst. 0
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 57 company confidential november 2011 ? 57 4.3.3 eee capability device address = 3 offset: 0x14 (hex) 4.3.4 eee wake error counter device address = 3 offset: 0x16 (hex) bit name description 15:3 reserved mode ro always 0. hw rst. 0 sw rst. 0 2 1000bt eee mode ro eee is supported for 1000base-t. hw rst. 1 sw rst. 1 1 100bt eee mode ro eee is supported for 100base-t. hw rst. 1 sw rst. 1 0 reserved mode ro always 0. hw rst. 0 sw rst. 0 bit name description 15: eee wake error counter mode ro count wake time faults where the phy fails to complete its normal wake sequence within the time required for the specific phy type. this counter is clear after read , and hold at all ones in the case of overflow. hw rst. 0 sw rst. 0
58 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 58 ? november 2011 company confidential 4.3.5 wake-on-lan loc_mac_addr_o device address = 3 offset: 0x804a (hex) 4.3.6 wake-on-lan loc_mac_addr_o device address = 3 offset: 0x804b (hex) 4.3.7 wake-on-lan loc_mac_addr_o device address = 3 offset: 0x804c (hex) bit name description 15:0 loc_mac_ addr_o[47:32] mode r/w bits [47:32] of local mac address, used in wake-on-lan. hw rst. 0 sw rst. retain bit name description 15:0 loc_mac_ addr_o[31:16] mode r/w bits [31:16] of local mac address, used in wake-on-lan. hw rst. 0 sw rst. retain bit name description 15:0 loc_mac_ addr_o[15:0] mode r/w bits [15:0] of local mac address, used in wake-on-lan. hw rst. 0 sw rst. retain
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 59 company confidential november 2011 ? 59 4.3.8 rem_phy_lpkb device address = 3 offset: 0x805a (hex) 4.3.9 smart_eee control1 device address = 3 offset: 0x805b (hex) 4.3.10 smart_eee control2 device address = 3 offset: 0x805c (hex) bit name description 15:1 reserved mode r/w hw rst. 0 sw rst. retain 0 rem_phy_lpbk mode r/w loopback receiv ed data packets to link partner hw rst. 0 sw rst. retain bit name description 15:8 lpi_wt mode r/w 1000bt tw timer. afte r timer done, buffered data will be send. lsb vs time : 1us default value: 17us. hw rst. 8?h11 sw rst. retain 7:0 lpi_wt mode r/w 100bt tw timer. after timer done, buffered data will be send. lsb vs time : 1us default value: 23us. hw rst. 8?h17 sw rst. retain bit name description 15:0 lpi_time[15:0] mode r/w lpi_ti mer will count when no da ta for transmission. after lpi_timer done, phy will enter lpi mode. lsb vs time : 163.84us default value: 335.544ms. hw rst. 16?h800 sw rst. retain
60 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 60 ? november 2011 company confidential 4.3.11 smart_eee control3 device address = 3 offset: 0x805d (hex) device address = 7, address ofset = 0x8016 (hex) device address = 7 offset: 0x1 (hex) bit name description 15:14 reserved mode r/w hw rst. 0 sw rst. 0 13:12 lpi_tx_delay_sel mode r/w select ip g length inserted between packets. it's for debug. hw rst. 2?b01 sw rst. retain 11:9 reserved mode ro hw rst. 0 sw rst. 0 8 lpi_en mode r/w enable smart eee. 1 = enable, 0 = disable. hw rst. 1?b01 sw rst. retain 7:0 lpi_timer[23:16] mode r/w lpi_ti mer will count when no da ta for transmission. after lpi_timer done, phy will enter lpi mode. hw rst. 0 sw rst. retain 4:3 select_clk125m mode r/w clk _25m output clock select 00=25m 01=50m 10=62.5m 11=125m hw rst. 00 sw rst. retain bit name description 15:8 reserved mode ro hw rst. 0 sw rst. 0
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 61 company confidential november 2011 ? 61 4.3.12 an status device address = 7 offset: 0x16 (hex) 4.3.13 an xnp transmit1 device address = 7 offset: 0x17 (hex) 4.3.14 an xnp transmit2 device address = 7 offset: 0x18 (hex) 7 xnp_status mode ro 1 = both local device and link partner have indicated support for extended next page; 0 = extended next page shall not be used. hw rst. 0 sw rst. 0 6:0 reserved mode ro hw rst. 0 sw rst. 0 bit name description bit name description 15:0 xnp_22 mode r/w a write to this re gister set mr_next_page_loaded. hw rst. 15?h0 sw rst. retain bit name description 15:0 xnp_23 mode r/w hw rst. 15?h0 sw rst. retain bit name description 15:0 xnp_24 mode r/w hw rst. 15?h0 sw rst. retain
62 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 62 ? november 2011 company confidential 4.3.15 eee advertisement device address = 7 offset: 0x3c (hex) 4.3.16 eee lp advertisement device address = 7 offset: 0x3d (hex) bit name description 15:3 reserved mode ro always 0. hw rst. 0 sw rst. 0 2 eee_1000bt mode r/w if local device supports eee operation for 1000bt, and eee operation is desired, this bit shall be set to 1. hw rst. 1?b1 sw rst. retain 1 eee_100bt mode r/w if local device suppo rts eee operation for 100bt, and eee operation is desired, th is bit shall be set to 1. hw rst. 1?b1 sw rst. retain 0 reserved mode ro always 0. hw rst. 0 sw rst. 0 bit name description 15:3 reserved mode ro always 0. hw rst. 0 sw rst. 0 2 eee_1000bt mode ro 1 = link partner supports eee operation for 1000bt, and eee operation is desired; 0 = link partner does not support eee operation for 1000bt, or eee operation is not desired. hw rst. 0 sw rst. 0 1 eee_100bt mode ro 1 = link partner supports eee operation for 100bt, and eee operation is desired; 0 = link partner does not support eee operation for 100bt, or eee operation is not desired. hw rst. 0 sw rst. 0 0 reserved mode ro always 0. hw rst. 0 sw rst. 0
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 63 company confidential november 2011 ? 63 5. package dimensions the ar8035 is packaged in a 40 pin qfn. the body size is 5 mm x 5 mm. the package drawings and dimensions are provided in figure 5-1 and the following table. figure 5-1. package views
64 ? ar8035 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. 64 ? november 2011 company confidential table 5-1. package dimensions dimension label min nom max unit a 0.70 0.75 0.80 mm a1 0.00 0.02 0.05 mm a3 0.20 ref b 0.15 0.20 0.25 mm d 4.90 5.00 5.10 mm e 4.90 5.00 5.10 mm d2 3.15 3.30 3.50 mm e2 3.15 3.30 3.50 mm e 0.35 0.40 0.45 mm k0.20----mm l 0.30 0.40 0.50 mm r0.09----mm la 0.12 0.15 0.18 mm lb 0.23 0.26 0.29 mm lc 0.30 0.39 0.50 mm notes: 1. all dimensions refer to jedec standard mo-220 vhhe-1
atheros communications, inc. ar8035 integrated 10/100/1000 mbps ethernet transceiver ? 65 company confidential november 2011 ? 65 6. ordering information 7. top-side marking table 6-1. ar8035 ordering information ordering number version default ordering unit ar8035-al1a commercial tray pack ar8035-al1a-r commercial tape and reel ar8035-al1b-r industrial tape and reel table 7-1. ar8035 marking ordering number marking ar8035-al1a ar8035-al1a-r ar8035-a ar8035-al1b-r 8035-al1b figure 7-1. ar8035 top-side marking (commercial) ar8035-a figure 7-2. ar8035 top-side marking (industrial) 8035-al1b
company confidential subject to change without notice atheros communications, incorporated 1700 technology drive san jose, ca 95110 tel: 408.773.5200 fax: 408.773.9940 www.atheros.com ? 2010 by atheros communications, inc. all rights reserved. atheros ? , atheros driven ? , atheros xr ? , driving the wireless future ? , rocm ? , super a/g ? , super g ? , super n ? , total 802.11 ? , xspan ? , wireless future. unleashed now. ? , and wake on wireless ? are registered by atheros communications, inc. atheros sst?, signal- sustain technology?, the air is cleaner at 5-ghz?, and 5-up? are trademarks of atheros communications, inc. the atheros logo is a registered trademark of atheros communications, inc. all other trademarks are the property of their respective holders. subject to change without notice. document number: mk g-15827 rev. 2.0

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